The present invention relates to semiconductor integrated circuits, and more particularly to a data input/output line sensing circuit for transferring data read from a memory cell to a data output buffer and for amplifying data represented in the form of a voltage difference.
Recently, as the density of semiconductor memory devices has increased, the size of the unit memory cells has decreased. The reduction of the memory cell size requires a lower power supply voltage for protecting elements. For example, a power supply voltage of 3.3V is typically used in a dynamic RAM of the 64 Mbit class, while a power supply voltage of 5V is typically used in a dynamic RAM of the 16 Mbit class. However, a lower power supply voltage delays the time required for sensing data represented in the form of the voltage difference, because the lower power supply voltage leads to a reduced data voltage difference. Particularly, in a high density semiconductor memory, it is required to provide a data input/output line sensing circuit which can transfer data of a weak voltage difference read from a memory cell at a high speed to a data output buffer on the same chip.
FIG. 1 shows a conventional data input/output line sensing circuit employed in a 4 Mbit dynamic RAM made by the Samsung Co. Ltd. The circuit includes a first differential amplifier 70A, a second differential amplifier 70B, a precharge circuit 70C, a latch 70D and an output driver 70E. In FIG. 1, the data sensing operation is performed in two steps; one by the first differential amplifier 70A and the other by the second differential amplifier 70B. The first differential amplifier 70A, the second differential amplifier 70B and the precharge circuit 70C are all enabled or disabled by a signal .phi.S which is generated with a predetermined time delay after column gate transistors for connecting/disconnecting bit lines with data input/output lines are turned on. The signal .phi.S is generally known in the art as a sensing circuit actuating signal. In the conventional circuit, the signal .phi.S is at the logic "low" state before the data input/output line sensing circuit is enabled. This turns off the respective pull-down transistors 10 and 30 in the first and second differential amplifier 70A and 70B, thereby disabling the sensing operation. However, precharge transistors 42 and 44 in precharge circuit 70C are turned on, thereby providing the "high" state to input lines of latch 70D. Consecutively, the outputs of latch 70D are held at the "low" level. At a result, output driver 70E is kept at a high impedance state or tri-state. In the meantime, when the data input/output line sensing circuit is enabled, signal .phi.S is changed to the "high" level. Then, precharge transistors 42 and 44 of precharge circuit 70C are turned off. Memory data is read from a cell array (not shown), causing a voltage difference in the voltage levels at the input/output lines IO and IO. The voltage difference between the input/output lines IO and IO is then amplified by the first differential amplifier 70A, and the amplified voltage difference output at lines 62 and 64 is again differentially amplified by the second differential amplifier 70B. The voltage difference between lines 66 and 68 is fully developed to the CMOS level. Further, depending upon the voltage levels of lines 66 and 68, complementary output data DO and DO is output through the output driver 70E.
It is noted that in the conventional data input/output line circuit, the sensing operation is divided into two steps and current is consumed in each step. Therefore, the conventional circuit is disadvantageous because of the current consumption may. Further, since a sensing operation is performed in each step, the sensing operation cannot be performed at a high speed. Because of these problems, the conventional data input/output line sensing circuit is considered unsuitable for high density and high speed semiconductor memory devices with low current consumption.